A Matlab/SIMULINK toolbox for the simulation-based high-level synthesis of Nyquist-rate data converters-application to a pure digital 0.13 μm CMOS 12-bit@80 MS/s analog front-end for PLC/VDSL

This paper presents a toolbox for the time-domain simulation and optimization-based high-level synthesis of Nyquist-rate data converters in Matlab®. Behavioural models of building blocks, including their critical non-idealities, are incorporated into SIMULINK® as C-compiled S-functions. This approach significantly speeds up system-level simulations while keeping high accuracy and interoperability of different subcircuit models. Moreover, their combined use with an efficient optimizer makes the proposed toolbox a valuable alternative for the design of broadband communication analog front-ends. As a case study, an embedded 0.13 μm CMOS 12 bit@80 MS/s A/D/A interface for PLC and VDSL is synthesized to show the capabilities of the presented tool.