A statistical power estimation methodology embedded in a SystemC code translator

This work describes a methodology for estimating switching activity, which is needed to evaluate power dissipation. The methodology is integrated in a VHDL to SystemC translation process and therefore needs no additional source modifications by the user. The SystemC model is favoured to allow a homogeneous system simulation environment, which speeds up the simulation. The translation process further implements an approach to wrap RTL to transaction level interfaces so that the translated module can be connected to a system level simulator. The switching analysis is based on a statistical model of the underlying HW structure and a preceding analysis of the input dataset. The accuracy and speed-up of the approach is finally illustrated and compared to conventional steps of a power analysis flow.