Processor evaluation cube : A classification and survey of processor evaluation techniques

Selecting appropriate hardware resources corresponding to the application is an important task for design of an embedded system or a SoC. A large number of techniques have been proposed in literatu ...

[1]  Margaret Martonosi,et al.  Challenges in Computer Architecture Evaluation , 2003, Computer.

[2]  Vladimir D. Živković.  From High Level Application Specification to System-level Architecture Definition : Exploration , Design and Compilation , 2002 .

[3]  Axel Jantsch,et al.  Networks on chip , 2003 .

[4]  Amer Baghdadi,et al.  Design space exploration for hardware/software codesign of multiprocessor systems , 2000, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668).

[5]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[6]  Ed F. Deprettere,et al.  A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach , 2001, Embedded Processor Design Challenges.

[7]  Anshul Kumar,et al.  Automatic synthesis of system on chip multiprocessor architectures for process networks , 2004, CODES+ISSS '04.

[8]  Martti Forsell,et al.  Fast processor core selection for WLAN modem using mappability estimation , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

[9]  Krzysztof Kuchcinski,et al.  Time-energy design space exploration for multi-layer memory architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[10]  Soonhoi Ha,et al.  A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling , 1999, CODES '99.

[11]  Michael J. Flynn,et al.  Some Computer Organizations and Their Effectiveness , 1972, IEEE Transactions on Computers.

[12]  Miodrag Potkonjak,et al.  System Synthesis of Synchronous Multimedia Applications , 1999, TECS.

[13]  Miodrag Potkonjak,et al.  Exploring the diversity of multimedia systems , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Alberto L. Sangiovanni-Vincentelli,et al.  A compilation-based software estimation scheme for hardware/software co-simulation , 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).

[15]  Andrew S. Cassidy,et al.  Layered, multi-threaded, high-level performance design , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[16]  Paolo Giusto,et al.  Reliable estimation of execution time of embedded software , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[17]  Niraj K. Jha,et al.  MOCSYN: multiobjective core-based single-chip system synthesis , 1999, DATE '99.

[18]  Ed F. Deprettere,et al.  Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS , 2002 .

[19]  Doug Burger,et al.  Measuring Experimental Error in Microprocessor Simulation , 2001, ISCA 2001.

[20]  Jeffry T. Russell,et al.  Architecture-level performance evaluation of component-based embedded systems , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[21]  Sharad Malik,et al.  A disciplined approach to the development of platform architectures , 2002 .

[22]  Sharad Malik,et al.  Processor evaluation in an embedded systems design environment , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[23]  Todd M. Austin,et al.  SimpleScalar: An Infrastructure for Computer System Modeling , 2002, Computer.

[24]  Daniel P. Siewiorek,et al.  Automatic configuration of embedded multicomputer systems , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Sharad Malik,et al.  Retargetable static timing analysis for embedded software , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[26]  Soonhoi Ha,et al.  A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling , 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).

[27]  Anshul Kumar,et al.  ASIP design methodologies: survey and issues , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

[28]  Wayne H. Wolf.  A Decade of Hardware/Software Codesign , 2003, Computer.

[29]  W. Rosenstiel,et al.  Static timing analysis of embedded software on advanced processor architectures , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[30]  Luigi Carro,et al.  A Design Methodology for Embedded Systems based on Multiple Processors , 2000, DIPES.

[31]  Martti Forsell.  Advanced Simulation Environment for Shared Memory Network-on-Chips , 2002 .