Monotonicity and run-time scheduling

Modern embedded multi-processors can execute several stream-processing applications concurrently. Typically, these applications are partitioned into tasks that communicate over buffers together forming a task graph. The fact that these applications are started and stopped by the user combined with the knowledge that not all applications are necessarily completely characterised makes it attractive to use run-time scheduling. We define and characterise a class of budget schedulers that by construction bound the interference from other applications. Furthermore, we will show that the worst-case effects of these schedulers can be included in dataflow process networks. The execution of the resulting dataflow process network is shown to result in tight and conservative bounds on the end-to-end temporal behaviour of the execution of the task graph on a cycle-true simulator. Given that the inter-task synchronisation of the application allows for a dataflow model that is functionally deterministic, this enables exploration of various buffer capacities and scheduler settings at a high level of abstraction.

[1]  Sharad Malik,et al.  Performance analysis of real-time embedded software , 1997 .

[2]  Rolf Ernst,et al.  Performance analysis for complex embedded applications , 2005, Int. J. Embed. Syst..

[3]  Axel Jantsch,et al.  Flow regulation for on-chip communication , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[4]  Giorgio Buttazzo,et al.  Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications , 1997 .

[5]  Aloysius K. Mok,et al.  A multiframe model for real-time tasks , 1996, 17th IEEE Real-Time Systems Symposium.

[6]  Gerard J. M. Smit,et al.  Modelling run-time arbitration by latency-rate servers in dataflow graphs , 2007, SCOPES '07.

[7]  Edward A. Lee,et al.  Dataflow process networks , 1995, Proc. IEEE.

[8]  Giorgio C. Buttazzo,et al.  HARD REAL-TIME COMPUTING SYSTEMS Predictable Scheduling Algorithms and Applications , 2007 .

[9]  Lothar Thiele,et al.  Complex task activation schemes in system level performance analysis , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[10]  Kees G. W. Goossens,et al.  C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems , 2002, Des. Autom. Embed. Syst..

[11]  Marco Bekooij,et al.  Performance Guarantees by Simulation of Process Networks. , 2005 .

[12]  Kees G. W. Goossens,et al.  Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis , 2009, IET Comput. Digit. Tech..

[13]  Rene L. Cruz,et al.  A calculus for network delay, Part II: Network analysis , 1991, IEEE Trans. Inf. Theory.

[14]  Adam Donlin,et al.  Transaction level modeling: flows and use models , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..

[15]  Jean A. Peperstraete,et al.  Cycle-static dataflow , 1996, IEEE Trans. Signal Process..

[16]  Giorgio C. Buttazzo,et al.  Resource Reservation in Dynamic Real-Time Systems , 2004, Real-Time Systems.

[17]  Lui Sha,et al.  Aperiodic task scheduling for Hard-Real-Time systems , 2006, Real-Time Systems.

[18]  Kang G. Shin,et al.  Integrating Virtual Execution Platform for Accurate Analysis in Distributed Real-Time Control System Development , 2007, 28th IEEE International Real-Time Systems Symposium (RTSS 2007).

[19]  Andreas Gerstlauer,et al.  RTOS modeling for system level design , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[20]  Anujan Varma,et al.  Latency-rate servers: a general model for analysis of traffic scheduling algorithms , 1996, Proceedings of IEEE INFOCOM '96. Conference on Computer Communications.

[21]  Alberto L. Sangiovanni-Vincentelli,et al.  Implementing Synchronous Models on Loosely Time Triggered Architectures , 2008, IEEE Transactions on Computers.

[22]  Sander Stuijk,et al.  Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[23]  Marco Bekooij,et al.  Performance guarantees by simulation of process , 2005, SCOPES '05.

[24]  Gerard J. M. Smit,et al.  Efficient Computation of Buffer Capacities for Cyclo-Static Dataflow Graphs , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[25]  Maarten Wiggers,et al.  A Priority-Based Budget Scheduler with Conservative Dataflow Model , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[26]  Rolf Ernst,et al.  Design space exploration and system optimization with SymTA/S - symbolic timing analysis for systems , 2004, 25th IEEE International Real-Time Systems Symposium.

[27]  Erwin A. de Kock,et al.  YAPI: application modeling for signal processing systems , 2000, Proceedings 37th Design Automation Conference.

[28]  Shuvra S. Bhattacharyya,et al.  Embedded Multiprocessors: Scheduling and Synchronization , 2000 .

[29]  Marco Spuri,et al.  Scheduling aperiodic tasks in dynamic priority systems , 1996, Real-Time Systems.

[30]  Gerard J. M. Smit,et al.  Buffer Capacity Computation for Throughput Constrained Streaming Applications with Data-Dependent Inter-Task Communication , 2008, 2008 IEEE Real-Time and Embedded Technology and Applications Symposium.