A graph-theoretic approach to the IC layout resizing problem

Based on the topological and geometric properties of polygons, an efficient IC layout resizing algorithm is developed. The algorithm has the following features: 1) it operates on the IC layout data base and generates the resized layout data base which is acceptable to the patterngeneration programs or the electron-beam programs; 2) it can efficiently handle large and complex IC layouts; and 3) it produces no gaps and no overlappings in the resized layout data base.