Modern implementation of a realtime 3D beamformer and scan converter system

This paper describes a high-speed 3D parallel beamformer and scan conversion system for a 5.0MHz 2D curved phased array transducer. The system uses Field Programmable Gate Array (FPGA)s to implement 288 receive channels. Each channel contains a 4ksample circular RAM buffer, delay calculation unit, interpolation unit, and apodization unit. The FPGA accepts a 12 bit parallel signal from 65MS/s ADCs, while internal processing clocks run at 200MHz. The imaged region was selected in order to minimize FPGA hardware requirements while providing minimal loss in image quality. Eighty image lines are produced synchronously, each with 246 axial points per line. The beamformer is capable of a sustained throughput of 100M beamformed samples/s. An onboard PCI interface transfers the processed data to PC RAM for scan conversion. A Graphic Processing Unit (GPU) shader program performs the envelope detection, scan conversion, and image display in real time. The design was tested by comparing computer simulations of the gate array design with a theoretical model of the beamformer. Two- way radiation pattern simulations show the sidelobes produced by the beamformer roll off to approximately -73 dB, for an ideal point target at 200 wavelengths. Routed hardware timing results allow for processing clock speeds of up to 282MHz - almost a third faster then our target clock speed. Keywords-Beamformer, FPGA, 3D, Real-time