Recurrence equations and the optimization of synchronous logic circuits

The authors present a formulation for the problem of optimizing synchronous logic across register boundaries. They describe the degrees of freedom that are the don't-care conditions of an embedded subnetwork by means of sets of execution traces, described implicitly by synchronous recurrence equations. The optimization problem reduces to that of finding minimum-cost solutions to such equations. An exact solution algorithm for this problem is presented, along with approximations that improve its computational efficiency. The feasibility and effectiveness of the approach were demonstrated on synchronous benchmark circuits.<<ETX>>

[1]  Yahiko Kambayashi,et al.  The Transduction Method-Design of Logic Networks Based on Permissible Functions , 1989, IEEE Trans. Computers.

[2]  A. Sangiovanni-Vincentelli,et al.  A synthesis and optimization procedure for fully and easily testable sequential machines , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Charles E. Leiserson,et al.  Optimizing Synchronous Circuitry by Retiming (Preliminary Version) , 1983 .

[4]  Giovanni De Micheli,et al.  Don't care set specifications in combinational and synchronous logic circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[6]  Fabio Somenzi,et al.  An iterative algorithm for the binate covering problem , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[7]  J. Hartmanis.  Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics) , 1966 .

[8]  Wayne Wolf,et al.  High-Level VLSI Synthesis , 1991 .

[9]  David L. Dill,et al.  Trace theory for automatic hierarchical verification of speed-independent circuits , 1989, ACM distinguished dissertations.

[10]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[11]  E. McCluskey.  Minimization of Boolean functions , 1956 .

[12]  Sujit Dey,et al.  Partitioning sequential circuits for logic optimization , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[13]  Gabriele Saucier,et al.  ASYL: A Rule-Based System for Controller Synthesis , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Srinivas Devadas,et al.  Decomposition and factorization of sequential finite state machines , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  G. De Micheli,et al.  Synthesis and optimization of synchronous logic circuits from recurrence equations , 1992, [1992] Proceedings The European Conference on Design Automation.

[16]  J. Hartmanis,et al.  Algebraic Structure Theory Of Sequential Machines , 1966 .

[17]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[18]  Willard Van Orman Quine,et al.  The Problem of Simplifying Truth Functions , 1952 .

[19]  Giovanni De Micheli,et al.  Synchronous logic synthesis: algorithms for cycle-time minimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Vishwani D. Agrawal,et al.  STATE ASSIGNMENT FOR INITIALIZABLE SYNTHESIS , 1989 .

[21]  Edward A. Feigenbaum,et al.  Switching and Finite Automata Theory: Computer Science Series , 1990 .

[22]  Robert K. Brayton,et al.  An exact minimizer for Boolean relations , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[23]  Vishwani D. Agrawal,et al.  State assignment for initializable synthesis (gate level analysis) , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[24]  Robert K. Brayton,et al.  Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Jan L. A. van de Snepscheut,et al.  Trace theory and the definition of hierarchical components , 1983 .

[26]  Giovanni De Micheli,et al.  Control optimization based on resynchronization of operations , 1991, 28th ACM/IEEE Design Automation Conference.

[27]  Nripendra N. Biswas,et al.  Minimization of Boolean Functions , 1971, IEEE Transactions on Computers.

[28]  Robert K. Brayton,et al.  Retiming and resynthesis: optimizing sequential networks with combinational techniques , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[29]  Wayne Wolf,et al.  Architectural Optimization Methods for Control-Dominated Machines , 1991 .

[30]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.