Dynamic and Partial FPGA Exploitation

Today's field programmable gate array (FPGA) architectures, like Xilinx's Virtex-II series, enable partial and dynamic run-time self-reconfiguration. This feature allows the substitution of parts of a hardware design implemented on this reconfigurable hardware, and therefore, a system can be adapted to the actual demands of applications running on the chip. Exploiting this possibility enables the development of adaptive hardware for a huge variety of applications. A novel method for communication interfaces using look up table (LUT)-based communication primitives enables an exact separation of reconfigurable parts and a fast and intelligent bus-system. A new adaptive software/hardware reconfigurable system is presented in this paper, using a real application in the automotive domain implemented on a Xilinx Virtex-II 3000 FPGA to present results

[1]  Klaus D. Müller-Glaser,et al.  Automotive Control Unit Optimisation Perspectives: Body Functions on-Demand by Dynamic Reconfiguration , 2005 .

[2]  Jürgen Becker,et al.  Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs , 2005, ARCS Workshops.

[3]  Jürgen Becker,et al.  Configurable systems-on-chip (CSoC) , 2002, Proceedings. 15th Symposium on Integrated Circuits and Systems Design.

[4]  Jürgen Becker,et al.  Configware and morphware going mainstream , 2003, J. Syst. Archit..

[5]  Jürgen Teich,et al.  Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration , 2004, IEEE International Parallel and Distributed Processing Symposium.

[6]  Jürgen Becker,et al.  Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

[7]  Jan M. Rabaey,et al.  Reconfigurable processing: the solution to low-power programmable DSP , 1997, 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[8]  Reiner W. Hartenstein,et al.  A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[9]  Scott McMillan,et al.  A lightweight approach for embedded reconfiguration of FPGAs , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[10]  Jürgen Becker,et al.  Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations , 2003, VLSI-SOC.

[11]  Ashish Tewari.  Modern Control Design With MATLAB and SIMULINK , 2002 .

[12]  Jürgen Becker,et al.  Dynamic Adaptive Routing Techniques In Multigrain Dynamic Reconfigurable Hardware Architectures , 2004 .

[13]  Patrick Lysaght.  Future design tools for platform FPGAs , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[14]  Lars Braun,et al.  Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems , 2004, FPL.

[15]  Donal Heffernan,et al.  Expanding Automotive Electronic Systems , 2002, Computer.

[16]  Rudy Lauwereins,et al.  Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs , 2002, FPL.

[17]  Jürgen Becker,et al.  An FPGA run-time system for dynamical on-demand reconfiguration , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[18]  Jonathan Rose,et al.  CALL FOR ARTICLES IEEE Design & Test of Computers Special Issue on Microprocessors , 1996 .

[19]  Jürgen Becker,et al.  Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics , 2005, ReCoSoC.

[20]  V. Baumgarte,et al.  PACT XPP-A Self-Reconfigurable Data Processing Architecture , 2001 .

[21]  Markus Weinhardt,et al.  PACT XPP—A Self-Reconfigurable Data Processing Architecture , 2004, The Journal of Supercomputing.

[22]  Scott Hauck,et al.  Reconfigurable computing: a survey of systems and software , 2002, CSUR.

[23]  J. Becker,et al.  Real-time configuration code decompression for dynamic FPGA self-reconfiguration , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..