Chip editor: Leveraging circuit edit for logic obfuscation and trusted fabrication

The globalization of the semiconductor foundry business poses grave risks in terms of intellectual property (IP) protection, especially for critical applications. Over the past few years, several techniques have been proposed that allow manufacturing of ICs at untrusted foundries by obfuscating and/or locking, albeit at high design overhead, low security guarantees and high cost. In this paper, for the first time, we utilize well-known, low-cost circuit edit techniques, which enable a designer to modify a circuit post-fabrication on a chip-by-chip basis. In the proposed design flow, obfuscated ICs are fabricated and tested at untrusted foundries, and post-fabrication focused ion beam (FIB) circuit edit techniques are utilized to revert the circuit back to its intended functionality at a trusted design house. In order to obfuscate the structural logic of the design, several possible gate-level techniques such as wire swapping and gate insertion are proposed. At the same time, the tradeoffs between layout-level modifications to aid circuit edit and the strength of obfuscation provided by the proposed approach are also assessed. Gate-level simulation results show that the chip-editor flow provides a strong level of design obfuscation and makes it infeasible for the untrusted foundry to retrieve the original design from the obfuscated layout it receives and the resultant netlist it can extract.