Area efficient floating-point adder and multiplier with IEEE-754 compatible semantics

In this paper we describe an open source floating-point adder and multiplier implemented using a 36-bit custom number format based on radix-16 and optimized for the 7-series FPGAs from Xilinx. Although this number format is not identical to the single-precision IEEE-754 format, the floatingpoint operators are designed in such a way that the numerical results for a given operation will be identical to the result from an IEEE-754 compliant operator with support for round-to-nearest even, NaNs and Infs, and subnormal numbers. The drawback of this number format is that the rounding step is more involved than in a regular, radix-2 based operator. On the other hand, the use of a high radix means that the area cost associated with normalization and denormalization can be reduced, leading to a net area advantage for the custom number format, under the assumption that support for subnormal numbers is required. The area of the floating-point adder in a Kintex-7 FPGA is 261 slice LUTs and the area of the floating-point multiplier is 235 slice LUTs and 2 DSP48E blocks. The adder can operate at 319 MHz and the multiplier can operate at a frequency of 305 MHz.

[1]  Martin Langhammer,et al.  FPGA Floating Point Datapath Compiler , 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.

[2]  Martin Langhammer.  Floating point datapath synthesis for FPGAs , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[3]  M.K. Jaiswal,et al.  Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA , 2008, 2008 IEEE Region 10 and the Third international Conference on Industrial and Information Systems.

[4]  Sigal Asaf,et al.  FPgen - a test generation framework for datapath floating-point verification , 2003, Eighth IEEE International High-Level Design Validation and Test Workshop.

[5]  An Independent Analysis of Floating-point DSP Design Flow and Performance on Altera 28-nm FPGAs , 2012 .

[6]  Florent de Dinechin,et al.  Designing Custom Arithmetic Data Paths with FloPoCo , 2011, IEEE Design & Test of Computers.

[7]  Brent E. Nelson,et al.  Higher radix floating-point representations for FPGA-based arithmetic , 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

[8]  Peter-Michael Seidel.  High-radix implementation of IEEE floating-point addition , 2005, 17th IEEE Symposium on Computer Arithmetic (ARITH'05).

[9]  F. D. Dinechin,et al.  Custom Arithmetic Datapath Design for FPGAs using the FloPoCo Core Generator , 2011 .

[10]  Madeleine Englund.  Hybrid Floating-point Units in FPGAs , 2012 .

[11]  Arun Paidimarri,et al.  FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation , 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.