Evolutionary Compilation to Long Instruction Superscalar Microarchitectures for Exploiting Parallelism At All Levels

VLIW seeks to perform all prediction before run-time, if possible. Superscalar hopes it can get reasonable performance even if the compiler disappears. Let's assume the solution includes dynamic scheduling hardware (superscalar), but with explicit parallelism expressed in the ISA (i.e., an EPIC ISA). The compiler's predictions via profiling are input dependent, and are assumed to hold true for the entire life of the program. Common sense tells us that programs are used differently even by the same user (say as the user transitions to a "power user"). The hardware predictions are very accurate, but the potential parallelism exploited by them is limited to a small distance (the size of the hardware window). So the compiler has the right scope (large), but poor prediction. The hardware has great prediction, but terrible scope. There has been a war raging between the two approaches. Instead of warring, it is tempting to try to combine the two. I propose that we add some levels to the current, rather stunted hierarchy of parallelism exploitation.