3D photonics as enabling technology for deep 3D DRAM stacking

3D stacking improves bandwidth, energy, and latency of DRAMs by exploiting shorter and more abundant wiring in three dimensions. While future stacks are predicted to provide tens of DRAM layers, TSV pitches are bound to stop decreasing due to physical limitations, requiring either large area overheads or energy for higher pin data rates to preserve bandwidth scaling. In addition, deep 3D DRAM stacks increase the average number of TSVs hops to reach the appropriate DRAM layer. Recent advances in vertical silicon-photonic interconnects now allow diameters of 1-2μm which results in high bandwidth density for optics. In this paper, we explore the benefits and architectural implications of vertical optical interconnects in terms of area, power, and performance. We propose a hierarchical approach to stacking 3D DRAM to tens of layers by utilizing sub-stacks which are optically-interconnected to a memory interface on the processor die. Our results show that photonics could be a key enabler for deep-3D DRAM offering at least 2× interconnect area savings compared to TSVs for the same bandwidth with comparable performance and less power.