Power and data for a wireless implanted neural recording system

This paper reports a two-way communication and inductive power link for a neural recording system. For this system a telemetry circuit was designed which utilizes an Integer-N PLL to support multiple outward data channels. The PLL design consumes less than 1.3mW below 100MHz, uses self-biasing techniques for supply rejection, has dimensions of 350um × 680um, and generates frequencies with a phase noise of -83dBc/Hz @100kHz offset, as measured at 80MHz. A wireless demonstration of the implanted circuitry is presented. Wireless powering is achieved with the help of a Class E Converter and demodulation of ASK data sent from the implant at 10Mbps is achieved with a simple asynchronous receiver.

[1]  W. Liu,et al.  A 128-Channel 6 mW Wireless Neural Recording IC With Spike Feature Extraction and UWB Transmitter , 2009, IEEE Transactions on Neural Systems and Rehabilitation Engineering.

[2]  Behzad Razavi,et al.  Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS , 1995, IEEE J. Solid State Circuits.

[3]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[4]  Glenn A. DeMichele,et al.  Inductively-coupled power and data link for neural prostheses using a class-E oscillator and FSK modulation , 2003, Proceedings of the 25th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (IEEE Cat. No.03CH37439).

[5]  Thomas H. Lee,et al.  The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES , 2003 .

[6]  R.R. Harrison,et al.  Wireless Neural Recording With Single Low-Power Integrated Circuit , 2009, IEEE Transactions on Neural Systems and Rehabilitation Engineering.

[7]  Brian Ellis.  The Design of CMOS Radio-Frequency Integrated Circuits , 2004 .