Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

This paper presents an error tolerant hardware efficient VLSI architecture for bit parallel systolic multiplication over dual base, which can be pipelined. This error tolerant architecture is well suited to VLSI implementation because of its regularity, modular structure, and unidirectional data flow. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35um CMOS technology. This architecture can also operate over both the dual-base and polynomial base.

[1]  Richard E. Blahut,et al.  Fast Algorithms for Digital Signal Processing , 1985 .

[2]  Chin-Liang Wang,et al.  Systolic array implementation of multipliers for finite fields GF(2/sup m/) , 1991 .

[3]  M. Benaissa,et al.  Dual basis systolic multipliers for GF(2m) , 1997 .

[4]  S.T.J. Fenn,et al.  Bit-serial dual basis systolic multipliers for GF(2/sup m/) , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[5]  Dhiraj K. Pradhan,et al.  C-testable bit parallel multipliers over GF(2m) , 2008, TODE.

[6]  Mohammed Benaissa,et al.  A dual basis bit-serial systolic multiplier for GF(2m) , 1995, Integr..

[7]  Kee-Young Yoo,et al.  A new digit-serial systolic multiplier for finite fields GF(2/sup m/) , 2001, 2001 International Conferences on Info-Tech and Info-Net. Proceedings (Cat. No.01EX479).

[8]  Trieu-Kien Truong,et al.  A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases , 1988, IEEE Trans. Computers.

[9]  Elwyn R. Berlekamp,et al.  Bit-serial Reed - Solomon encoders , 1982, IEEE Transactions on Information Theory.

[10]  Mohammed Benaissa,et al.  GF(2^m) Multiplication and Division Over the Dual Basis , 1996, IEEE Trans. Computers.

[11]  M. Benaissa,et al.  Generalised triangular basis multipliers for the design of Reed-Solomon codecs , 1997, 1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing.

[12]  T. Gulliver,et al.  The generation of rimitive olynomials in GF(q) with independent roots and their applications for ower residue codes, VLSI testing and finite field multipliers using normal basis , 1991 .

[13]  Soonhak Kwon,et al.  A Digit-Serial Multiplier for Finite Field , 2005 .

[14]  Vijay K. Bhargava,et al.  Division and bit-serial multiplication over GF(qm) , 1992 .

[15]  Berk Sunar,et al.  Mastrovito Multiplier for All Trinomials , 1999, IEEE Trans. Computers.

[16]  Christof Paar,et al.  Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography , 2006, IEEE Transactions on Computers.

[17]  Mohammed Benaissa,et al.  Division over GF(2/sup m/) , 1992 .

[18]  C.-L. Wang,et al.  Digit-serial systolic multiplier for finite fields GF(2m) , 1998 .

[19]  Xuemin Chen,et al.  Error-Control Coding for Data Networks , 1999 .

[20]  Trieu-Kien Truong,et al.  Systolic Multipliers for Finite Fields GF(2m) , 1984, IEEE Transactions on Computers.

[21]  Soonhak Kwon,et al.  A digit-serial multiplier for finite field GF(2/sup m/) , 2005, IEEE Trans. Very Large Scale Integr. Syst..