A Scalable and Minimized Butterfly Fat Tree (SMBFT) Switching Network for On-Chip Communication

This study proposes a scalable and cost effective Network on Chip (NoC) based architecture that is a modified version of Butterfly Fat Tree (BFT) network and is known as Scalable and Minimized Butterfly Fat Tree (SMBFT) switching network. The corresponding floor plan and scalable routing algorithm for the proposed network is also presented. Component Based Interconnection Network Simulator (CINSIM) was used to evaluate the steady state as well as transient behaviors of SMBFT, BFT and Binary Tree switching networks for average delay at targets. Results show that the proposed on-chip network outperforms the other two in terms of average delay, area and cost. SMFBT also comprises of less number of routers, links and levels. Hence the proposed network of switches is superior to BFT and Binary Tree and can efficiently be used for on-chip communication networks.

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