Statistical timing analysis using bounds and selective enumeration

The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper, we propose a new approach to statistical timing analysis which uses statistical bounds and selective enumeration to refine these bounds. First, we provide a formal definition of the statistical delay of a circuit and derive a statistical timing analysis method from this definition. Since this method for finding the exact statistical delay has exponential run time complexity with circuit size, we also propose a new method for computing statistical bounds which has linear run time complexity. We prove the correctness of the proposed bounds. Since we provide both a lower and upper bound on the true statistical delay, we can determine the quality of the bounds. If the computed bounds are not sufficiently close to each other, we propose the use of a heuristic to iteratively improve the bounds using selective enumeration of the sample space with additional run time. The proposed methods were implemented and tested on benchmark circuits. The results demonstrate that the proposed bounds have only a small error, which could be further reduced using selective enumeration with modest additional run time.

[1]  J.D. Meindl,et al.  Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[2]  Ying Liu,et al.  Assessment of true worst case circuit performance under interconnect parameter variations , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

[3]  Nagisa Ishiura,et al.  Probabilistic CTSS: analysis of timing error probability in asynchronous logic circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[4]  Feller William,et al.  An Introduction To Probability Theory And Its Applications , 1950 .

[5]  Sharad Malik,et al.  Statistical timing analysis of combinational circuits , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[6]  Kurt Keutzer,et al.  Getting to the bottom of deep submicron , 1998, ICCAD '98.

[7]  A. Gattiker,et al.  Timing yield estimation from static timing analysis , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

[8]  Sani R. Nassif,et al.  A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance , 2000, Proceedings 37th Design Automation Conference.

[9]  S. Nassif,et al.  Delay variability: sources, impacts and trends , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[10]  Ibrahim N. Hajj,et al.  Static timing analysis including power supply noise effect on propagation delay in VLSI circuits , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[11]  Norman P. Jouppi,et al.  Timing Analysis for nMOS VLSI , 1983, 20th Design Automation Conference Proceedings.

[12]  Michel R. C. M. Berkelaar,et al.  Gate sizing using a statistical delay model , 2000, DATE '00.

[13]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Sani R. Nassif,et al.  Modeling and analysis of manufacturing variations , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[15]  Ying Liu,et al.  Model order-reduction of RC(L) interconnect including variational analysis , 1999, DAC '99.

[16]  M. Berkelaar,et al.  Statistical delay calculation, a linear time method , 1997 .

[17]  Andrew B. Kahng,et al.  Subwavelength optical lithography: challenges and impact on physical design , 1999, ISPD '99.

[18]  Rung-Bin Lin,et al.  A new statistical approach to timing analysis of VLSI circuits , 1998, Proceedings Eleventh International Conference on VLSI Design.

[19]  Sharad Malik,et al.  Statistical timing optimization of combinational logic circuits , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[20]  Kwang-Ting Cheng,et al.  Fast statistical timing analysis by probabilistic event propagation , 2001, DAC '01.

[21]  Edwin H.-M. Sha,et al.  Optimizing circuits with confidence probability using probabilistic retiming , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[22]  M. Ray Mercer,et al.  Predicting circuit performance using circuit-level statistical timing analysis , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[23]  Sachin S. Sapatnekar,et al.  A timing model incorporating the effect of crosstalk on delay andits application to optimal channel routing , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  Malgorzata Marek-Sadowska,et al.  Crosstalk in VLSI interconnections , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Robert B. Hitchcock,et al.  Timing Verification and the Timing Analysis Program , 1982, 19th Design Automation Conference.

[26]  Kurt Keutzer,et al.  Miller factor for gate-level coupling delay calculation , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[27]  Kwang-Ting Cheng,et al.  False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation , 2002, DAC '02.

[28]  Andrew B. Kahng,et al.  On switch factor based analysis of coupled RC interconnects , 2000, Proceedings 37th Design Automation Conference.

[29]  Kenneth L. Shepard,et al.  Noise in deep submicron digital design , 1996, Proceedings of International Conference on Computer Aided Design.

[30]  S. Nassif,et al.  Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[31]  Kurt Keutzer,et al.  Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[32]  Ibrahim N. Hajj,et al.  Probabilistic simulation for reliability analysis of CMOS VLSI circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[33]  Kurt Keutzer,et al.  A general probabilistic framework for worst case timing analysis , 2002, DAC '02.