Pipelined Architecture for a Radix-2 Fast Walsh–Hadamard–Fourier Transform Algorithm

This brief proposes an efficient radix-2 single-path delay commutator (SDC) pipelined architecture to implement the fast Walsh-Hadamard-Fourier transform (FWFT) algorithm. The proposed architecture includes (log2 N - 1) SDC stages, which are implemented by merged half-butterfly. The merged half-butterfly is proposed to achieve 100% hardware utilization and minimum buffer usage by sharing common merged half-butterflies in the time-multiplexed approach. Compared with the conventional pipelined radix-2 FFT+Walsh-Hadamard Transform (WHT) designs, the proposed architecture reduces the number of buffers by 50% and of adders by 25%. The required number of complex multipliers is decreased to 0.5 log2 N - 0.5, which is roughly the minimum number. Moreover, the proposed architecture can be applied to FFT/WHT/sequence-ordered complex Hadamard transform (SCHT).

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