Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions

Speculative execution refers to the execution of parts of a computation before the execution of the conditional operations that decide whether it needs to be executed. It has been shown to be a promising technique for eliminating performance bottlenecks imposed by control flow in hardware and software implementations alike. In this paper, we present techniques to incorporate speculative execution in a fine-grained manner into scheduling of control-how intensive behavioral descriptions. We demonstrate that failing to take into account information such as resource constraints and branch probabilities can lead to significantly sub-optimal performance. We also demonstrate that it may be necessary to speculate simultaneously along multiple paths, subject to resource constraints, in order to minimize the delay overheads incurred when prediction errors occur. Experimental results on several benchmarks show that our speculative scheduling algorithm can result in significant (up to seven-fold) improvements in performance (measured in terms of the average number of clock cycles) as compared to scheduling without speculative execution. Also, the best and worst case execution times for the speculatively performed schedules are the same as or better than the corresponding values for the schedules obtained without speculative execution.

[1]  Markku Renfors,et al.  The maximum sampling rate of digital filters under hardware speed constraints , 1981 .

[2]  Kemal Ebcioglu,et al.  A compilation technique for software pipelining of loops with conditional jumps , 1987, MICRO 20.

[3]  Scott Mahlke,et al.  Sentinel scheduling: a model for compiler-controlled speculative execution , 1993 .

[4]  Joseph A. Fisher,et al.  Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.

[5]  Scott A. Mahlke,et al.  Three Architecutral Models for Compiler-Controlled Speculative Execution , 1995, IEEE Trans. Computers.

[6]  Norman P. Jouppi,et al.  How useful are non-blocking loads, stream buffers and speculative execution in multiple issue processors? , 1995, Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture.

[7]  Kazutoshi Wakabayashi,et al.  Global scheduling independent of control dependencies based on condition vectors , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[8]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[9]  Kenneth C. Yeager The Mips R10000 superscalar microprocessor , 1996, IEEE Micro.

[10]  Monica S. Lam,et al.  Limits of control flow on parallelism , 1992, ISCA '92.

[11]  Alok Sharma,et al.  Empirical evaluation of some high-level synthesis scheduling heuristics , 1991, 28th ACM/IEEE Design Automation Conference.

[12]  Elizabeth M. Rudnick,et al.  Enhancing high-level control-flow for improved testability , 1996, ICCAD 1996.

[13]  Rolf Ernst,et al.  Experiments with low-level speculative computation based on multiple branch prediction , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Sujit Dey,et al.  Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications , 1994, 31st Design Automation Conference.

[15]  F. Warren Burton,et al.  Speculative computation, parallelism, and functional programming , 1985, IEEE Transactions on Computers.

[16]  Chong-Min Kyung,et al.  FAMOS: an efficient scheduling algorithm for high-level synthesis , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Niraj K. Jha,et al.  : a novel scheduling technique for control-flow intensive behavioral descriptions , 1997, ICCAD 1997.

[18]  Louise Trevillyan,et al.  Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[19]  Rolf Ernst,et al.  Combining MBP-speculative computation and loop pipelining in high-level synthesis , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[20]  Raul Camposano,et al.  Path-based scheduling for synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Edward M. Riseman,et al.  The Inhibition of Potential Parallelism by Conditional Jumps , 1972, IEEE Transactions on Computers.

[22]  J. Tatemura Speculative parallelism of intelligent interactive systems , 1995, Proceedings of IECON '95 - 21st Annual Conference on IEEE Industrial Electronics.

[23]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  Rolf Ernst,et al.  Register synthesis for speculative computation , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[25]  Vicki H. Allan,et al.  An Approach to Combine Predicated/Speculative Execution for Programs with Unpredictable Branches , 1994, Parallel Architectures and Compilation Techniques.

[26]  David G. Messerschmitt,et al.  Breaking the Recursive Bottleneck , 1988 .

[27]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[28]  Forrest Brewer,et al.  A new symbolic technique for control-dependent scheduling , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..