Test Compression for Dynamically Reconfigurable Processors

We present the world’s first test compression technique that features automation of compression rules for test time reduction on dynamically reconfigurable processors. Evaluations on an actual 40-nm product show that our technique achieves a 2.7 times compression ratio for original configuration information (better than does GZIP), the peak decompression bandwidth of 1.6 GB/s, and 2.7 times shorter test times.

[1]  Tulika Mitra,et al.  Configuration bitstream compression for dynamically reconfigurable FPGAs , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[2]  Mehdi Baradaran Tahoori,et al.  Test Compression for FPGAs , 2006, 2006 IEEE International Test Conference.

[3]  Sorin Cotofana,et al.  Bitstream compression techniques for Virtex 4 FPGAs , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[4]  Hiroaki Inoue,et al.  Test Compression for Dynamically Reconfigurable Processors , 2010, FPL.

[5]  Viktor K. Prasanna,et al.  Configuration compression for FPGA-based embedded systems , 2005, IEEE Trans. Very Large Scale Integr. Syst..

[6]  David A. Wood,et al.  Frequent Pattern Compression: A Significance-Based Compression Scheme for L2 Caches , 2004 .

[7]  Shahin Toutounchi,et al.  FPGA test and coverage , 2002, Proceedings. International Test Conference.

[8]  Rudy Lauwereins,et al.  Architecture exploration for a reconfigurable architecture template , 2005, IEEE Design & Test of Computers.

[9]  Shurong Chen,et al.  Partial Reconfiguration Bitstream Compression for Virtex FPGAs , 2008, 2008 Congress on Image and Signal Processing.

[10]  Jose L Nunez-Yanez,et al.  Gigabyte per second streaming lossless data compression hardware based on a configurable variable-geometry CAM dictionary , 2006 .

[11]  Jürgen Teich,et al.  Hardware Decompression Techniques for FPGA-Based Embedded Systems , 2009, TRETS.

[12]  G. Blelloch Introduction to Data Compression * , 2022 .

[13]  S. Jones,et al.  Design and performance of a main memory hardware data compressor , 1996, Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies.

[14]  Tadahiro Kuroda,et al.  MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[15]  Zhiyuan Li,et al.  Configuration Compression for Virtex FPGAs , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[16]  Guido Masera,et al.  A new approach to compress the configuration information of programmable devices , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[17]  Zhiyuan Li,et al.  Configuration compression for the Xilinx XC6200 FPGA , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[18]  Hideharu Amano,et al.  Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device , 2003, FPL.