19PMlC-6 Design of Logarithmic Encoder and Error Corrections

This paper presents a design of binary logarithm or logarithm radix-2 encoder. An implementation of overall circuits using combinational logic only and based on Mitchell’s approximation algorithm. The generated error by the Mitchell’s algorithm is analyzed and is used to develop a method to design of error correction circuits in order to improve the accuracy of the result. The area and speed characteristics of proposed circuits design can be shown using an EPFlOK20RC240-4 Altera FPGA for implementing. Finally, the error correction circuits that is used to reduce the error in the resulting logarithm approximation can be evaluated and comparison in resulting percentage of error to show the performance of error correction circuits.