Performance Estimation: IPC

Performance estimation of a processor can easily lead to a large saving in time, which would otherwise be spent on time consuming simulations. Poor choice of processor can lead to an expensive design due to either the choice of an expensive processor or due to a large hardware as the selected processor severely under performs. In this work, we estimate the IPC (instructions per cycle) of the processor for a particular application. We propose a technique to estimate the upper and lower limit of IPC for a given application. Experimental results indicate that IPC can be estimated within about 20% accuracy without using time consuming instruction set simulators.

[1]  鈴木 敬,et al.  Efficient Software Performance Estimation Methods for Hardware/Software Codesign , 1996 .

[2]  S. Devadas,et al.  ISDL: An Instruction Set Description Language For Retargetability , 1997, Proceedings of the 34th Design Automation Conference.

[3]  Vikram S. Adve,et al.  LLVM: a compilation framework for lifelong program analysis & transformation , 2004, International Symposium on Code Generation and Optimization, 2004. CGO 2004..

[4]  Rajat Moona,et al.  Processor modeling for hardware software codesign , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[5]  Sharad Malik,et al.  Processor evaluation in an embedded systems design environment , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[6]  Subhash Chandra,et al.  Retargetable functional simulator using high level processor models , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[7]  Todd M. Austin,et al.  SimpleScalar: An Infrastructure for Computer System Modeling , 2002, Computer.

[8]  Amer Baghdadi,et al.  Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems , 2002, IEEE Trans. Software Eng..

[9]  Markus Freericks,et al.  Describing instruction set processors using nML , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[10]  Reinhold Heckmann,et al.  Worst case execution time prediction by static program analysis , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[11]  Peter Pirsch,et al.  A platform-independent methodology for performance estimation of streaming media applications , 2002, Proceedings. IEEE International Conference on Multimedia and Expo.

[12]  Peter Puschner.  Is Worst-Case Execution-Time Analysis a Non-Problem? — Towards New Software and Hardware Architectures , 2002 .

[13]  Wu Jigang,et al.  Estimating processor performance of library function , 2005, Second International Conference on Embedded Software and Systems (ICESS'05).

[14]  Wu Jigang,et al.  Practical techniques for performance estimation of processors , 2005, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05).

[15]  Rajat Moona,et al.  Processor models for retargetable tools , 2000, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668).