PLL Based on Self-Biased Techniques

Delay-Iorked loop (DLL) and phase-Iorked loop (PLJ") designs based upon self-biased techniques are presented. The DLL and PLL designs achieve process technology inde­ pendence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancel­ lation, and, most importantly, low input tracking jitter. Both the damping factor and the bandwidth to operating frequency ratio areIetermined cmpletely by a ratio of capacitances, Self-biasing aVOids the necessity for external biasing, which can require special bandgap bias circuits, by generating all of the internal bias voltages and currents from each other so that the bias levels are eomJletely determined by the operating conditions. Fabricated in a 0.5-llm )V -well CMOS gate array process, the PLL achieves an operating frequency range of 0.0025 MHz to 550 MHz and input tracking jitter of 384 ps at 250 MHz with 500 m V of low frequency square wave supply noise.