IMPLEMENTATION OF DEBLOCKING FILTER ALGORITHM USING RECONFIGURABLE ARCHITECTURE

A new international standards H.264 is used for the compression of video images, the blocking artifacts is one of the artifacts in video and image compression coding. This artifact will reduce the picture quality of the reconstructed images and video. To improve the quality of the received picture Deblocking filters are used to remove the artifacts. There are several algorithms have been proposed by researchers, this paper will introduce a Deblocking algorithm to remove the artifacts. This paper also proposes the hardware implementation for same algorithm. To reduce the power consumption of hardware implementation a technique clock gating is introduced. We achieved the result of 30% power reduction for clock gating technique at the cost of 2.3 % hardware and 5.8% clock speed.