Pipelines with internal buffers

Concurrent or overlapped processing of more than one task is a common technique used in many computer architectures to increase the throughput. A pipeline is one such form consisting of a set of hardware segments which can be operated in an overlapped fashion. The existing and many proposed pipelines assume that a task must flow synchronously, without wait or preemption, from segment to segment for its execution. In this paper we propose a pipeline model in which priority buffers are provided at every segment to control the flow of tasks. Several different priority implementations are analyzed assuming periodic arrivals of tasks. The characteristics studied are, queue size, wait time and throughput. It is shown that the theoretical maximum throughput of a pipeline is attainable with the use of internal buffers. Moreover, it is shown that a substantial degree of freedom in scheduling of tasks is achieved by these methods.