The Effect of Gate

Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. When a resistive (non-zero) fault model is used in fault detection, the gate orientation plays an important role. In this work, we discuss how a logically symmetrical gate may show an electronically non-symmetrical behavior and how such property influences fault detection and test pattern generation of digital VLSI circuits.

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