A digital array based bit serial processor for arbitrary window size kernel convolution in vision sensors

Abstract The high speed and in-pixel processing of image data in smart vision sensors is an important solution for real time machine vision tasks. Diverse architectures have been presented for array based kernel convolution processing, many of which use analog processing elements to save space. In this paper a digital array based bit serial architecture is presented to perform certain image filtering tasks in the digital domain and hence gain higher accuracies than the analog methods. The presented method benefits from more diverse convolution options such as arbitrary size kernel windows, compared with the digital pulse based approaches. The proposed digital cell structure is compact enough to fit inside an image sensor pixel. When incorporated in a vision chip, resolutions of up to 12 bit accuracy can be obtained in kernel convolution functions with 35×28 μm 2 layout area usage per pixel in a 90 nm technology. Still, higher accuracies can be obtained with larger pixels. The power consumption of the approach is approximately 10 nW/pixel at a frame rate of 1 kfps.

[1]  Mehdi Habibi,et al.  Analysis, Enhancement, and Sensitivity Improvement of the Correlation Image Sensor , 2012, IEEE Transactions on Instrumentation and Measurement.

[2]  David Stoppa,et al.  A CMOS image sensor with programmable pixel-level analog processing , 2005, IEEE Transactions on Neural Networks.

[3]  Stanislaw Szczepanski,et al.  An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Bernabé Linares-Barranco,et al.  An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors , 2012, IEEE Journal of Solid-State Circuits.

[5]  Tobi Delbrück,et al.  Event-Based Pixel Sensitive to Changes of Color and Brightness , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Ákos Zarándy,et al.  Approaching object detector mouse retina circuit model analysis and implementation on cellular sensor‐processor array , 2012, Int. J. Circuit Theory Appl..

[7]  Hongbo Zhu,et al.  A real-time motion-feature-extraction image processor employing digital-pixel-sensor-based parallel architecture , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[8]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[9]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[10]  Christofer Toumazou,et al.  A CMOS image sensor with spiking pixels for retinal stimulation , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[11]  Pei-Yung Hsiao,et al.  Generic 2-D gaussian smoothing filter for noisy image processing , 2007, TENCON 2007 - 2007 IEEE Region 10 Conference.

[12]  Amine Bermak,et al.  A DPS array with programmable resolution and reconfigurable conversion time , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Andreas G. Andreou,et al.  A scalable and programmable simplicial CNN digital pixel processor architecture , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  Luis Carranza,et al.  ACE16k based stand-alone system for real-time pre-processing tasks , 2005, SPIE Microtechnologies.

[15]  Antonio J. Plaza,et al.  Use of FPGA or GPU-based architectures for remotely sensed hyperspectral image processing , 2013, Integr..

[16]  Carlos Carreras,et al.  A complete dynamic power estimation model for data-paths in FPGA DSP designs , 2012, Integr..

[17]  Przemyslaw Brylski,et al.  FPGA implementation of parallel digital image processor , 2010, Signal Processing Algorithms, Architectures, Arrangements, and Applications SPA 2010.

[18]  Stephan Henker,et al.  A 32 GBit/s communication SoC for a waferscale neuromorphic system , 2012, Integr..

[19]  Amine Bermak,et al.  Adaptive-Quantization Digital Image Sensor for Low-Power Image Compression , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[20]  A. Bermak,et al.  A digital pixel sensor array with programmable dynamic range , 2005, IEEE Transactions on Electron Devices.

[21]  R. Schott,et al.  Efficient FPGA implementation of steerable Gaussian smoothers , 2012, Proceedings of the 2012 44th Southeastern Symposium on System Theory (SSST).

[22]  Xinqiao Liu,et al.  A 10000 frames/s CMOS digital pixel sensor , 2001, IEEE J. Solid State Circuits.