Self-adjusting mechanism to dynamically suppress the effect of PVT variations on clock skew
暂无分享,去创建一个
[1] Nasser A. Kurd,et al. A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor , 2001, IEEE J. Solid State Circuits.
[2] Hao Yu,et al. Useful-skew clock optimization for multi-power mode designs , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[3] Jeng-Liang Tsai,et al. Statistical timing analysis driven post-silicon-tunable clock-tree synthesis , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[4] Jeng-Liang Tsai,et al. A yield improvement methodology using pre- and post-silicon statistical clock scheduling , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[5] Eby G. Friedman,et al. Clock distribution networks in synchronous digital integrated circuits , 2001, Proc. IEEE.
[6] Shiyan Hu,et al. Unified adaptivity optimization of clock and logic signals , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.
[7] Shih-Hsu Huang,et al. PVT-variations-tolerant clock design using self-correcting adjustable delay buffers , 2014, 2014 International Symposium on Next-Generation Electronics (ISNE).
[8] S. Ravi,et al. Clock Skew Optimization in Pre and Post CTS , 2012, 2012 International Conference on Advances in Computing and Communications.
[9] Sachin S. Sapatnekar,et al. Timing Analysis and Optimization of Sequential Circuits , 1998 .
[10] Wing-Kai Hon,et al. Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.
[11] Shih-Hsu Huang,et al. Low-power timing closure methodology for ultra-low voltage designs , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[12] Ankur Srivastava,et al. Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] Chun-Yuan Cheng,et al. An improved SAR controller for DLL applications , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[14] S. Naffziger,et al. Clock distribution on a dual-core, multi-threaded Itanium/sup /spl reg//-family processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..