VLSI Processor Architecture
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[1] Norman P. Jouppi,et al. MIPS: a VLSI processor architecture , 1981 .
[2] Bruce Wallace Leverett. Register Allocation in Optimizing Compilers , 1983 .
[3] Norman P. Jouppi,et al. Design of a high performance VLSI processor , 1983 .
[4] Gene McDaniel,et al. An Instruction Fetch Unit for a High-Performance Personal Computer , 1984, IEEE Transactions on Computers.
[5] Douglas W. Clark,et al. Performance of the VAX-11/780 translation buffer: simulation and measurement , 1985, TOCS.
[6] David Robson,et al. Smalltalk-80: The Language and Its Implementation , 1983 .
[7] Leonard Jay Shustek,et al. Analysis and performance of computer instruction sets , 1978 .
[8] Carlo H. Séquin,et al. Strategies for Managing the Register File in RISC , 1983, IEEE Transactions on Computers.
[9] Martin Hopkins,et al. An overview of the PL.8 compiler , 1982, SIGP.
[10] Maurice V. Wilkes,et al. The Cambridge CAP computer and its operating system (Operating and programming systems series) , 1979 .
[11] A. J. Rainal. Computing inductive noise of chip packages , 1984, AT&T Bell Laboratories Technical Journal.
[12] Michael J. Flynn,et al. Execution Architecture: The DELtran Experiment , 1983, IEEE Transactions on Computers.
[13] James R. Larus. A comparison of microcode, assembly code, and high-level languages on the VAX-11 and RISC I , 1982, CARN.
[14] Michael J. Flynn,et al. Directions and Issues in Architecture and Language , 1980, Computer.
[15] Emmanuel Katevenis,et al. Reduced instruction set computer architectures for VLSI , 1984 .
[16] Norman P. Jouppi,et al. Organization and VLSI implementation of MIPS , 1984 .
[17] Butler W. Lampson,et al. Fast procedure calls , 1982, ASPLOS I.
[18] Thomas R. Gross,et al. Optimizing delayed branches , 1982, MICRO 15.
[19] Fred C. Chow,et al. A portable machine-independent global optimizer--design and measurements , 1984 .
[20] Ronald Fagin,et al. Cold-start vs. warm-start miss ratios , 1978, CACM.
[21] R. D. Davies. Solid state: The case for CMOS: Its low power consumption and many design choices mean that by the decade's end, half of all ICs may be made by this technique , 1983, IEEE Spectrum.
[22] Glenford J. Myers,et al. The case against stack-oriented instruction sets , 1977, CARN.
[23] Justin R. Rattner,et al. Hardware/software cooperation in the iAPX-432 , 1982, ASPLOS I.
[24] Charles L. Seitz,et al. Concurrent VLSI Architectures , 1984, IEEE Transactions on Computers.
[25] Gerald Jay Sussman,et al. Scheme-79 - Lisp on a Chip , 1981, Computer.
[26] David A. Patterson,et al. The case for the reduced instruction set computer , 1980, CARN.
[27] William A. Wulf. Compilers and Computer Architecture , 1981, Computer.
[28] Lynn Conway,et al. Introduction to VLSI systems , 1978 .
[29] W. Johnson. A VLSI superminicomputer CPU , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[30] R. C. Eden,et al. Solid state: Integrated circuits: The case for gallium arsenide: This superfast semiconductor holds great promise for high-speed computers, and manufacturing difficulties are now beginning to be overcome , 1983, IEEE Spectrum.
[31] D. Dobberpuhl,et al. A 32b microprocessor with on chip virtual memory management , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[32] David R. Ditzel,et al. Register allocation for free: The C machine stack cache , 1982, ASPLOS I.
[33] R. Schumann,et al. A 32b bus interface chip , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[34] Carlo H. Séquin,et al. A VLSI RISC , 1982, Computer.
[35] Thomas Karl Richard Gross,et al. Code optimization of pipeline constraints , 1983 .
[36] Henry M. Levy,et al. Measurement and analysis of instruction use in the VAX-11/780 , 1982, ISCA 1982.
[37] Tom Gunter,et al. Microsystems a Microprocessor Architecture for a Changing World: The Motorola 68000 , 1979, Computer.
[38] Douglas W. Clark,et al. Cache Performance in the VAX-11/780 , 1983, TOCS.
[39] John Cocke,et al. Register Allocation Via Coloring , 1981, Comput. Lang..
[40] Richard L. Sites. How to Use 1000 Registers , 1979 .
[41] Richard K. Johnsson,et al. An overview of the mesa processor architecture , 1982, ASPLOS I.
[42] Mervyn Jack,et al. Introduction to MOS LSI design , 1983 .
[43] George Radin,et al. The 801 minicomputer , 1982, ASPLOS I.
[44] Scott P. Wakefield,et al. Studies in execution architectures , 1982 .
[45] John L. Hennessy. A language for microcode description and simulation in VLSI , 1980 .
[46] David A. Patterson,et al. Architecture of SOAR: Smalltalk on a RISC , 1984, ISCA '84.
[47] Thomas R. Gross,et al. Postpass Code Optimization of Pipeline Constraints , 1983, TOPL.
[48] Robert S. Fabry,et al. Capability-based addressing , 1974, CACM.
[49] Norman P. Jouppi,et al. Hardware/software tradeoffs for increased performance , 1982, ASPLOS I.
[50] John L. Hennessy,et al. Register allocation by priority-based coloring , 1984, SIGPLAN '84.