Power-aware sourse feedback single-ended 7T SRAM cell at nanoscale regime

This article presents a low power and highly stable source feedback SE7T (single-ended 7T) SRAM cell. Using Monte-Carlo simulations critical design metrics of proposed SE7T SRAM cell are estimated and the estimated results are compared with that of conventional 6T SRAM cell and conventional 7T SRAM cell (CONV7T). The proposed source feedback single Ended (SE7T) SRAM cell achieves 8.6 ×/12.5 × and 1.2 ×/5.3 × lower write power and hold power as compared to CONV6T/CONV7T respectively. The proposed bitcell takes 1.3 × longer but 1.3 × less Read Access Time (TRA) as compared to CONV6T and CONV7T at 200 mV respectively. The proposed bitcell also provides 1.67 × and 1.07 × higher read stability and write ability as compared to 6T SRAM Cell.

[1]  Alexander Fish,et al.  A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM) , 2011, IEEE Journal of Solid-State Circuits.

[2]  K. Ishibashi,et al.  A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits , 2007, IEEE Journal of Solid-State Circuits.

[3]  Saraju P. Mohanty,et al.  PVT-tolerant 7-Transistor SRAM Optimization via Polynomial Regression , 2011, 2011 International Symposium on Electronic System Design.

[4]  Tughrul Arslan,et al.  Variation resilient subthreshold SRAM cell design technique , 2012 .

[5]  Jia Di,et al.  A pFET-access radiation-hardened SRAM for extreme environments , 2008, 2008 51st Midwest Symposium on Circuits and Systems.

[6]  H. Fujiwara,et al.  Which is the best dual-port SRAM in 45-nm process technology? — 8T, 10T single end, and 10T differential — , 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

[7]  Benton H. Calhoun,et al.  Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[8]  K. Roy,et al.  A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM , 2007, IEEE Journal of Solid-State Circuits.

[9]  Bruno Allard,et al.  Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell , 2012, 2012 International SoC Design Conference (ISOCC).

[10]  Anantha Chandrakasan,et al.  Challenges and Directions for Low-Voltage SRAM , 2011, IEEE Design & Test of Computers.

[11]  Mohd. Hasan,et al.  A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell , 2012, Microelectron. Reliab..

[12]  Soumitra Pal,et al.  Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.