Design Technology of Stacked Type Chain PRAM

[1]  Kunishima,et al.  High-density chain ferroelectric random-access memory (CFRAM) , 1997, Symposium 1997 on VLSI Circuits.

[2]  Dong Woo Kim,et al.  Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory , 2006, 2009 Symposium on VLSI Technology.

[3]  Kimiyoshi Usami,et al.  Automated low-power technique exploiting multiple supply voltages applied to a media processor , 1998 .

[4]  Shigeyoshi Watanabe.  Impact of three-dimensional transistor on the pattern area reduction for ULSI , 2003 .

[5]  Jungdal Choi,et al.  3D approaches for non-volatile memory , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[6]  Kinam Kim,et al.  A 0.18 /spl mu/m 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM) , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[7]  Y. Sasago,et al.  Phase-change memory driven by poly-Si MOS transistor with low cost and high-programming gigabyte-per-second throughput , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[8]  Y. Iwata,et al.  Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory , 2007, 2007 IEEE International Electron Devices Meeting.

[9]  Byung-Gil Choi,et al.  A 0.1-$\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation , 2007, IEEE Journal of Solid-State Circuits.