Processing Display System Architectures

Recent advances in the design of image processing and display equipment have occurred in two key areas, namely, data flow architectures and pipeline array processor architectures. Data flow involves the use of high speed data interfaces to the display processor, a flexible internal bus architecture, and efficient access to display processor memories. Image processing power is achieved through the use of pipeline processors rather than high-speed, large address-space, integral CPUs. Hardware constraints impact the design of algorithms which take advantage of the 70 nanosecond pixel rates and the computational power of the pipeline processors. The DeAnza Systems IP 8500 and IP 1172 image processing display systems exemplify architectural advances in data flow and pipeline processor architectures.