An 80 ns 1 Mbit MASK ROM with a new memory cell
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N. Endo | F. Masuoka | M. Ono | S. Ariizumi | T. Iwase
[1] H. Kawamoto,et al. A 1Mb ROM with on chip ECC for yield enhancement , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[2] F. Masuoka,et al. A high speed 2k × 8 bit NMOS static RAM with a new double poly-Si gate memory cell process , 1980, 1980 International Electron Devices Meeting.