67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process

A very low energy -consuming SRAM design based on single-ended cells is demonstrated in this work. To resolve poor SNM (static noise margin) of prior single-ended memory cells, the porposed SRAM cell is equipped with a pull-up PMOS and a high-Vthn NMOS foot switch such that the cell state is not bothered by noise when the suppy voltage is getting lowered. Moreover, a PFOS (Positive Feedback Op-Amp Sensing) circuit is added between bitlines (BL, BL) to reduce the read delay and generate full-swing output. Last but not least, a voltage mode select (VMS) circuit is added to each column to reduce the static power of unselected cells such that idle power is drastically reduced. The reason is that the a lower voltage able to keep the state of bits is applied to those unselected cells. Not only are detailed description and all-PVT-corner simulations provided to predict the low power performance, a 1-kb SRAM design based on the proposed cells with BIST (build-in self test) circuit is realized using typical 40-nm CMOS technology. The worst energy/access and energy/bit are found to be 67.5 fJ, and 2.1 fJ, respectively.

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