Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication

An autonomous-DVFS-enabled supply island architecture on network-on-chip platforms is proposed. This architecture exploits the temporal and spatial network traffic variations in minimizing the communication energy while constraining the latency and supply management overhead. Each island is equipped with autonomous DVFS mechanism, which traces the local and nearby network conditions. In quantitative simulations with various types of representative traffic patterns, this approach achieves greater energy efficiency than two other low-energy architectures (typically 10% - 27% lower energy). With autonomous supply management on a proper granularity as demonstrated in this study, the communication energy can be minimized in a scalable manner for many-core NoCs.

[1]  S. Borkar,et al.  An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[2]  C. R. Jesshope,et al.  High performance communications in processor networks , 1989, ISCA '89.

[3]  Radu Marculescu,et al.  Architecting voltage islands in core-based system-on-a-chip designs , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[4]  Samuel Williams,et al.  The Landscape of Parallel Computing Research: A View from Berkeley , 2006 .

[5]  Chi-Ying Tsui,et al.  Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[6]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[7]  John M. Cohn,et al.  Managing power and performance for System-on-Chip designs using Voltage Islands , 2002, ICCAD 2002.

[8]  Niraj K. Jha,et al.  Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  S. Narendra,et al.  A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package , 2005, IEEE Journal of Solid-State Circuits.

[10]  Radu Marculescu,et al.  Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[11]  Radu Marculescu,et al.  Energy- and performance-aware mapping for regular NoC architectures , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Meeta Sharma Gupta,et al.  System level analysis of fast, per-core DVFS using on-chip switching regulators , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[13]  Li Shang,et al.  Dynamic voltage scaling with links for power optimization of interconnection networks , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[14]  Christos Faloutsos,et al.  Data mining meets performance evaluation: fast algorithms for modeling bursty traffic , 2002, Proceedings 18th International Conference on Data Engineering.

[15]  Sharad Malik,et al.  Orion: a power-performance simulator for interconnection networks , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

[16]  Zhonghai Lu,et al.  Network-on-Chip Benchmarking Specification Part 2: Micro-Benchmark Specification Version 1.0 , 2008 .

[17]  J.A. Tierno,et al.  A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI , 2008, IEEE Journal of Solid-State Circuits.

[18]  Resve A. Saleh,et al.  Application-driven floorplan-aware voltage island design , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[19]  A. Chandrakasan,et al.  A 180mV FFT processor using subthreshold circuit techniques , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[20]  I-Min Liu,et al.  Post-placement voltage island generation under performance requirement , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[21]  Eylem Ekici,et al.  Energy-constrained task mapping and scheduling in wireless sensor networks , 2005, IEEE International Conference on Mobile Adhoc and Sensor Systems Conference, 2005..

[22]  Axel Jantsch,et al.  Adaptive Power Management for the On-Chip Communication Network , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

[23]  R. Harjani,et al.  A High Efficiency DC-DC Converter Using 2nH On-Chip Inductors , 2007, 2007 IEEE Symposium on VLSI Circuits.