Design of Reconfigurable Memory for Fast Network Packet Header Parsing

This paper investigates the use of reconfigurable memory for fast network packet processing. It is proposed that this is achieved with the addition of logic to the memory that allows direct access to non byteor word-aligned fields found in various packet header formats. The proposed packet header parsing hardware is made flexible by the use of FPGA re-configurability and is capable to provide singlecycle access to different-sized packet header fields, placed in the on-chip memory. The paper elaborates how this solution results with much faster packet processing and significant improvement of the overall network processing throughput.

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