Implementation of FM-Based Communication System with 3-Level Parallel Multiplier Structure for Fast Transmission Using FPGA

Any communication setup with the two individual hardware gives the best measure of real-time parameters like hardware, speed, total power consumption, etc. The research article deals with the implementation of a 3-level parallel multiplier structure, which can be used mainly for FM Broadcasting system. The proposed system has been implemented using communication between the two FPGAs. The message signal with 1 MHz frequency, 16-bit sample signal is generated by the Direct Digital Synthesizer (DDS) and is modulated with 10 MHz, 16-bit sampled carrier signal and transmitted over the channel. At the receiver, the signal is passed through a noise removal FIR filter and demodulated for the reconstruction of the original signal. The target of the design has included area and speed optimization as well. The system has been simulated on Xilinx ISE 14.7 and ModelSim 10.1 software coded in VHDL. Synthesis reports are generated from ChipScope Pro Tool with ARTIX-7 board FM communication analysis. The simulated resulted are verified for the FM range 88–108 MHz.