A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines

Asynchronous circuits are interesting alternatives for implementing ultra-low power systems but they are more challenging to design. This work provides methods for designers to specify, verify, and implement self-timed pipelines. The connection of standard primitives allows specifying a control circuit. A method to derive a Petri net based model of this circuit is presented. The modeled transactions are only those necessary at a high level for the circuit verification and performance analysis. Additionally, the proposed framework includes merge and split choice structures in the control circuit for further reducing the power consumption of the targeted systems. It is associated with a design flow which uses standard EDA tools. The paper presents two practical examples illustrating how this framework can be used to design low-power systems based on a datapath specification: a finite impulse response (FIR) filter and an advanced encryption standard (AES) cipher. The obtained asynchronous FIR is 20% smaller and consumes 30% less energy compared to the synchronous design. The obtained asynchronous AES is 2% larger but consumes three times less energy than its synchronous counterpart.

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