An improved RNS reverse converter for the {22n+1−1, 2n, 2n−1} moduli set

In this paper, we propose a novel high speed memoryless reverse converter for the moduli set {2²ⁿ⁺¹−1, 2ⁿ, 2ⁿ−1}. First, we simplify the traditional Chinese Remainder Theorem in order to obtain a reverse converter that only requires arithmetic mod-{2^2n+l −1). Second, we further improve the resulting architecture to obtain a purely adder based reverse converter. The proposed converter has a critical path delay of {7n + 7) Full Adders (FA) while the best state of the art converter for this moduli set requires (10n + 5) FA on the critical path. To validate these results, the converters are implemented in a Standard Cell 0.18-μm CMOS technology and the results assert that, on average, the proposed converter achieves about 19% delay reduction at the expense of less than 3% area increase.