Practical Implementation of a Low-Power Content-Addressable Memory
暂无分享,去创建一个
[1] T. Kobayashi,et al. A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture , 1992, 1992 Symposium on VLSI Circuits Digest of Technical Papers.
[2] Cheng-Wen Wu,et al. A Low-Power CAM Design for LZ Data Compression , 2000, IEEE Trans. Computers.
[3] Hisatada Miyatake,et al. A design for high-speed low-power CMOS fully parallel content-addressable memory macros , 2001 .
[4] Chein-Wei Jen,et al. Power modeling and low-power design of content addressable memories , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).
[5] J. C. Chang,et al. Design for low-power, low-cost, and high-reliability precomputation-based content-addressable memory , 2002, Asia-Pacific Conference on Circuits and Systems.
[6] Tarek Darwish,et al. Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[7] Aristides Efthymiou,et al. An adaptive serial-parallel CAM architecture for low-power cache blocks , 2002, ISLPED '02.
[8] Bin-Da Liu,et al. A low-power precomputation-based fully parallel content-addressable memory , 2003, IEEE J. Solid State Circuits.
[9] Bin-Da Liu,et al. Low-power and low-voltage fully parallel content-addressable memory , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..
[10] K. Pagiamtzis,et al. A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme , 2004, IEEE Journal of Solid-State Circuits.
[11] Andrew Mason,et al. A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).