A novel approach for and efficient implementation of 2 Level 2D DWT using ASIC and FPGA

In this paper, an efficient architecture called Modified Flipping is proposed. The implementation of 2 level 2D Discrete Wavelet Transform (DWT) is considered using Modified Flipping architecture. The System On Programmable Chip approach is adopted for the implementation of two level 2D DWT on Altera Field Programmable Gate Arrays based SOPC CYCLONE II EP2C35F672C6 kits with NIOS-II softcore processor. Modified flipping architecture and Flipping architecture are implemented using ASIC CADENCE TOOL of 180nm technology. From the implementation results, it is verified that the proposed Modified Flipping Architecture with MBW-PKCM increases the speed and reduce the hardware requirements. The proposed Modified flipping Architecture is operated with 6.8% higher speed compared with flipping Architecture. The hardware requirements are also 2% lesser compared to existing architecture. Pipelined registers required for MFA is 8.4% lesser than FA. Also for the sake of verification the proposed methods are verified using MATLAB R2009a. The corresponding output images for all the cases are given.

[1]  Mary Jane Irwin,et al.  VLSI architectures for the discrete wavelet transform , 1995 .

[2]  J.G. Delgado-Frias,et al.  A hybrid wave-pipelined network router , 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.

[3]  José G. Delgado-Frias,et al.  A hybrid wave pipelined network router , 2002 .

[4]  Stéphane Mallat,et al.  A Theory for Multiresolution Signal Decomposition: The Wavelet Representation , 1989, IEEE Trans. Pattern Anal. Mach. Intell..

[5]  Wei Li,et al.  A VLSI architecture for discrete wavelet transform , 1996, Proceedings of 3rd IEEE International Conference on Image Processing.

[6]  Liang-Gee Chen,et al.  VLSI implementation of shape-adaptive discrete wavelet transform , 2002, IS&T/SPIE Electronic Imaging.

[7]  G. Lakshminarayanan,et al.  Design and FPGA Implementation of Self Tuned Wavepipelined Filters , 2006 .

[8]  Liang-Gee Chen,et al.  Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform , 2004, IEEE Transactions on Signal Processing.

[9]  G. Lakshminarayanan,et al.  Design and FPGA implementation of image block encoders with 2D-DWT , 2003, TENCON 2003. Conference on Convergent Technologies for Asia-Pacific Region.

[10]  Chaitali Chakrabarti,et al.  Architectures for wavelet transforms: A survey , 1996, J. VLSI Signal Process..

[11]  Liang-Gee Chen,et al.  Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method , 2002, Asia-Pacific Conference on Circuits and Systems.

[12]  Stéphane Mallat,et al.  Multifrequency channel decompositions of images and wavelet models , 1989, IEEE Trans. Acoust. Speech Signal Process..

[13]  Jr. Earl E. Swartzlander,et al.  VLSI Signal Processing Systems , 1985 .

[14]  B. Venkataramani,et al.  Automation techniques for implementation of hybrid wave-pipelined 2D DWT , 2008, Journal of Real-Time Image Processing.

[15]  Wayne P. Burleson,et al.  A VLSI design methodology for distributed arithmetic , 1991, J. VLSI Signal Process..

[16]  Liang-Gee Chen,et al.  Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[17]  Ping-Sing Tsai,et al.  JPEG2000 Standard for Image Compression: Concepts, Algorithms and VLSI Architectures , 2004 .