Block processing structures for fixed point digital filtering

This work compares block processing structures using as a figure of merit the product of the chip area needed to implement the structure in NMOS and the reciprocal of the word rate. It considers both distributed arithmetic schemes and conventional multiplier implementation of block filters and compares these structures with conventional filter structures. By fixing the output signal quality of the filters one is able to find the best block processing configurations in terms of the assumed figure of merit.