Fast Algorithm and Low-Cost Hardware-Sharing Design of Multiple Integer Transforms for VC-1

In this brief, the fast 1D multiple integer transforms of Windows Media Video 9 (WMV-9/VC-1) are proposed by matrix decompositions, additions, and row/column permutations. Then, the proposed fast 1D integer transforms are hardware shared, and they can be applied to the 2D transform scheme. The hardware costs of the proposed fast 1D and 2D integer transform designs are smaller than those of the previous individual designs without shares. With the hardware share, the proposed architecture is suitable for the low-cost implementation of the VC-1 codec.

[1]  Sridhar Srinivasan,et al.  Computationally efficient transforms for video coding , 2005, IEEE International Conference on Image Processing 2005.

[2]  Shankar Regunathan,et al.  An overview of VC-1 , 2005, Visual Communications and Image Processing.

[3]  Chih-Peng Fan,et al.  Implementations of Low-Cost Hardware Sharing Architectures for Fast 8 x 8 and 4 x 4 Integer Transforms in H.264/AVC , 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[4]  Chih-Peng Fan,et al.  Efficient Fast 1-D 8$\,\times\,$8 Inverse Integer Transform for VC-1 Application , 2009, IEEE Transactions on Circuits and Systems for Video Technology.

[5]  T. Tran,et al.  The binDCT: fast multiplierless approximation of the DCT , 2000, IEEE Signal Processing Letters.

[6]  Seonyoung Lee,et al.  Design of Transform and Quantization Circuit for Multi-Standard Integrated Video Decoder , 2007, 2007 IEEE Workshop on Signal Processing Systems.

[7]  Jordi Ribas-Corbera,et al.  Windows Media Video 9: overview and applications , 2004, Signal Process. Image Commun..

[8]  Seonyoung Lee,et al.  Circuit implementation for transform and quantization operations of H.264/MPEG-4/VC-1 video decoder , 2007, 2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era.