A Novel 90nm 8T SRAM Cell With Enhanced Stability

As the MOSFETs channel length is scaling down, SRAM stability becomes the major concern for future technology. The cell becomes more susceptible to both process induced variation in device geometry and threshold voltage variability due to dopant fluctuation in the channel region. In this paper , a novel highly stable 8T SRAM cell is proposed which eliminates any noise induction during read operation and keeps the Read SNM as high as 415 mV at VDD = 1.2 V in 90 nm technology. The cell also supports low power operation at Cell VDD as low as 0.41 V. This new asymmetric cell structure is capable of using differential sense technique for high speed read operation.

[1]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[2]  Vivek De,et al.  Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[3]  A.P. Chandrakasan,et al.  Static noise margin variation for sub-threshold SRAM in 65-nm CMOS , 2006, IEEE Journal of Solid-State Circuits.

[4]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[5]  Pankaj Agarwal,et al.  A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[6]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[7]  Feipei Lai,et al.  Zero-aware asymmetric SRAM cell for reducing cache power in writing zero , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.