Architectural Power Estimation Based on Behavior Level Profiling

High level synthesis is the process of generating register transfer (RT) level designs from behavioral specifications. High level synthesis systems have traditionally taken into account such constraints as area, clock period and throughput time. Many high level synthesis systems [1] permit generation of many alternative RT level designs meeting these constraints in a relatively short time. If it is possible to accurately estimate the power consumption of RT level designs, then a low power design from among these alternatives can be selected.

[1]  James R. Larus,et al.  Optimally profiling and tracing programs , 1994, TOPL.

[2]  Mark Horowitz,et al.  IRSIM: An Incremental MOS Switch-Level Simulator , 1989, 26th ACM/IEEE Design Automation Conference.

[3]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[4]  W. G. Morris,et al.  CCG: a prototype coagulating code generator , 1991, PLDI '91.

[5]  Ranga Vemuri,et al.  DSS: a distributed high-level synthesis system , 1992, IEEE Design & Test of Computers.

[6]  Niraj K. Jha,et al.  Behavioral synthesis for low power , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[7]  Jan M. Rabaey,et al.  An integrated CAD system for algorithm-specific IC design , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Zachary J. Lemnios,et al.  Low-power electronics , 1994, IEEE Design & Test of Computers.

[9]  S. Katkoori,et al.  Profile-driven behavioral synthesis for low-power VLSI systems , 1995, IEEE Design & Test of Computers.

[10]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[11]  Miodrag Potkonjak,et al.  Optimizing power using transformations , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Farid N. Najm,et al.  A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[13]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[14]  Alan Dain Samples,et al.  Profile-Driven Compilation , 1991 .

[15]  Karl Pettis,et al.  Profile guided code positioning , 1990, PLDI '90.

[16]  Paul E. Landman,et al.  Low-power architectural design methodologies , 1995 .

[17]  Ranga Vemuri,et al.  High level profiling based low power synthesis technique , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[18]  J. Rabaey,et al.  Behavioral Level Power Estimation and Exploration , 1997 .

[19]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[20]  Vivek Sarkar,et al.  Determining average program execution times and their variance , 1989, PLDI '89.

[21]  Miodrag Potkonjak,et al.  HYPER-LP: a system for power minimization using architectural transformations , 1992, ICCAD.

[22]  David R. Ditzel,et al.  An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks , 1991 .

[23]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[24]  Niraj K. Jha,et al.  An ILP formulation for low power based on minimizing switched capacitance during data path allocation , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[25]  Miodrag Potkonjak,et al.  Fast prototyping of datapath-intensive architectures , 1991, IEEE Design & Test of Computers.

[26]  David A. Patterson,et al.  Reduced instruction set computers , 1985, CACM.

[27]  P. M. Chau,et al.  A model for estimating power dissipation in a class of DSP VLSI chips , 1991 .

[28]  Wayne Wolf,et al.  High-Level VLSI Synthesis , 1991 .

[29]  Jan M. Rabaey,et al.  Power estimation for high level synthesis , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[30]  Susan L. Graham,et al.  An execution profiler for modular programs , 1983, Softw. Pract. Exp..

[31]  William Stallings.  Reduced Instruction Set Computers , 1990 .

[32]  Farid N. Najm,et al.  Towards a high-level power estimation capability , 1995, ISLPED '95.