High-performance routing at the nanometer scale
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[1] Yao-Wen Chang,et al. Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability , 2007, 2007 Asia and South Pacific Design Automation Conference.
[2] Luciano Lavagno,et al. Electronic Design Automation for Integrated Circuits Handbook , 2006 .
[3] Muhammet Mustafa Ozdal,et al. Archer: a history-driven global routing algorithm , 2007, ICCAD 2007.
[4] Patrick Groeneveld,et al. Is probabilistic congestion estimation worthwhile? , 2005, SLIP '05.
[5] Chris C. N. Chu,et al. FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[6] Majid Sarrafzadeh,et al. Creating and exploiting flexibility in rectilinear Steiner trees , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Patrick Groeneveld,et al. Probabilistic congestion prediction , 2004, ISPD '04.
[8] Jason Cong,et al. MARS-a multilevel full-chip gridless routing system , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Keith So,et al. Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space , 2007, ISPD '07.
[10] Shashi Shekhar,et al. Multilevel hypergraph partitioning: applications in VLSI domain , 1999, IEEE Trans. Very Large Scale Integr. Syst..
[11] Sachin S. Sapatnekar,et al. A survey on multi-net global routing for integrated circuits , 2001, Integr..
[12] Martin D. F. Wong,et al. A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] Yao-Wen Chang,et al. Efficient obstacle-avoiding rectilinear steiner tree construction , 2007, ISPD '07.
[14] Jarrod A. Roy,et al. Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[15] Thomas H. Cormen,et al. Introduction to algorithms [2nd ed.] , 2001 .
[16] Jason Cong,et al. Multilevel approach to full-chip gridless routing , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).
[17] Raia Hadsell,et al. Improved global routing through congestion estimation , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[18] Majid Sarrafzadeh,et al. Pattern routing: use and theory for increasing predictability andavoiding coupling , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[19] Kun Yuan,et al. BoxRouter 2.0: architecture and implementation of a hybrid and robust global router , 2007, ICCAD 2007.
[20] Ronald L. Rivest,et al. Introduction to Algorithms , 1990 .
[21] David Z. Pan,et al. BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[22] Carl Ebeling,et al. PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.
[23] Andrew B. Kahng,et al. Highly scalable algorithms for rectilinear and octilinear Steiner trees , 2003, ASP-DAC '03.
[24] Christoph Albrecht,et al. Global routing by new approximation algorithms for multicommodityflow , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[25] Chris C. N. Chu,et al. Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design , 2005, ISPD '05.
[26] Jarrod A. Roy,et al. Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[27] Louis K. Scheffer. Physical CAD changes to incorporate design for lithography and manufacturability , 2004 .
[28] Ronald L. Rivest,et al. Introduction to Algorithms, Second Edition , 2001 .
[29] William A. Dees,et al. Automated Rip-Up and Reroute Techniques , 1982, DAC 1982.
[30] Chris C. N. Chu,et al. FastRoute 2.0: A High-quality and Efficient Global Router , 2007, 2007 Asia and South Pacific Design Automation Conference.
[31] Igor L. Markov,et al. On whitespace and stability in physical synthesis , 2006, Integr..
[32] David Z. Pan,et al. True crosstalk aware incremental placement with noise map , 2004, ICCAD 2004.
[33] Min Pan,et al. FastRoute: A Step to Integrate Global Routing into Placement , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[34] Kuang-Yao Lee,et al. Post-routing redundant via insertion for yield/reliability improvement , 2006, Asia and South Pacific Conference on Design Automation, 2006..
[35] Vaughn Betz,et al. VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.
[36] Joseph R. Shinnerl,et al. Multilevel optimization for large-scale circuit placement , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[37] Chris C. N. Chu,et al. Efficient rectilinear Steiner tree construction with rectilinear blockages , 2005, 2005 International Conference on Computer Design.
[38] Clifford Stein,et al. Introduction to Algorithms, 2nd edition. , 2001 .
[39] Minsik Cho,et al. Wire Density Driven Global Routing for CMP Variation and Timing , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.