A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS

A 33.6-to-33.8 Gb/s burst-mode CDR circuit is realized in 90nm CMOS technology. The LC gated VCO, the phase selector the input matching circuit, and the wideband data buffer are discussed. With 2n-1 PRBS input, the measured rms jitter for the recovered data is 1.15ps at 33.72Gb/s. This CDR can tolerate 31 consecutive identical bits with a locking time of 0.2ns (<7b interval). It consumes 73mW from a 1.2V supply excluding the buffers.

[1]  S. Kimura,et al.  A 10 Gb/s burst-mode CDR IC in 0.13 /spl mu/m CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[2]  Mihai Banu,et al.  A 660 Mb/s CMOS clock recovery circuit with instantaneous locking for NRZ data and burst-mode transmission , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[3]  B. Razavi,et al.  A 10 Gb/s CMOS clock and data recovery circuit with frequency detection , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).