On Database-Free Authentication of Microelectronic Components

Counterfeit integrated circuits (ICs) have become a significant security concern in the semiconductor industry as a result of the increasingly complex and distributed nature of the supply chain. These counterfeit chips may result in performance degradation, profit reduction, and reputation risk for the manufacturer. Therefore, developing effective countermeasures against such malpractices is becoming severely crucial. Physical unclonable function (PUF)-based authentication methods have the potential to mitigate these challenges. However, PUF-based solutions are restrained by several factors, such as additional design efforts and significant area/power overhead, struggle to maintain and update challenge–response pairs (CRPs) database, and the vulnerability to machine learning (ML) attacks. In this article, we address these challenges by developing a novel database-free and enrolment-free hardware authentication approaches, i.e., a digital watermark metric for ICs. To enable efficient database-free hardware integrity verification without enrolment, first, we transform the intrinsic variations in circuit parameters, e.g., boundary scan chain (BSC) path delays in the joint test action group (JTAG) chain into robust digital signatures. Then, we perform statistical analysis on a small pilot unit of authentic chips to create a robust watermark for a complete batch of chips, which jointly captures the characteristics of the physical layout, the manufacturing process, and the foundry. The increasing complexity in the current state-of-the-art designs makes it extremely hard for an adversary to perfectly clone such statistical characterization of circuit parameters using counterfeit or compromised hardware. Besides, the proposed approach requires no additional design or hardware overhead in IC design since it utilizes an embedded structure, which inherently exists within the chips. It also obviates the design house from characterizing each manufactured chip instance, reducing overall testing cost. A path-delay measurement method at a high resolution based on clock phase sweep is introduced to measure the delay values effectively. The proposed intrinsic identifier-based authentication approach is validated by performing emulation on FPGAs and also by conducting physical measurements on custom-made printed circuit boards (PCBs). The reliability of the generated watermarks is evaluated with environmental temperature fluctuations and the aging effect.

[1]  Swarup Bhunia,et al.  Robust counterfeit PCB detection exploiting intrinsic trace impedance variations , 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

[2]  Patrick Schaumont,et al.  A design method for remote integrity checking of complex PCBs , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[3]  Ingrid Verbauwhede,et al.  Machine learning attacks on 65nm Arbiter PUFs: Accurate modeling poses strict bounds on usability , 2012, 2012 IEEE International Workshop on Information Forensics and Security (WIFS).

[4]  Swarup Bhunia,et al.  Active protection against PCB physical tampering , 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

[5]  Takeshi Sugawara,et al.  An on-chip glitchy-clock generator for testing fault injection attacks , 2011, Journal of Cryptographic Engineering.

[6]  Yu Cao,et al.  Modeling and minimization of PMOS NBTI effect for robust nanometer design , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[7]  Mark Tehranipoor,et al.  System-Level Counterfeit Detection Using On-Chip Ring Oscillator Array , 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Swaroop Ghosh,et al.  How Secure Are Printed Circuit Boards Against Trojan Attacks? , 2015, IEEE Design & Test.

[9]  James F. Plusquellic,et al.  PUF-based authentication , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[10]  Srinivas Devadas,et al.  PUF Modeling Attacks on Simulated and Silicon Data , 2013, IEEE Transactions on Information Forensics and Security.

[11]  Swarup Bhunia,et al.  The Hardware Trojan War , 2018 .

[12]  Patrick Schaumont,et al.  A large scale characterization of RO-PUF , 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[13]  M. Rosenblatt A CENTRAL LIMIT THEOREM AND A STRONG MIXING CONDITION. , 1956, Proceedings of the National Academy of Sciences of the United States of America.

[14]  Lindsay I. Smith,et al.  A tutorial on Principal Components Analysis , 2002 .

[15]  Mark Mohammad Tehranipoor,et al.  SMA: A System-Level Mutual Authentication for Protecting Electronic Hardware and Firmware , 2017, IEEE Transactions on Dependable and Secure Computing.

[16]  Swarup Bhunia,et al.  An Intrinsic and Database-Free Authentication by Exploiting Process Variation in Back-End Capacitors , 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Swarup Bhunia,et al.  PiRA: IC authentication utilizing intrinsic variations in pin resistance , 2015, 2015 IEEE International Test Conference (ITC).

[18]  Daniel E. Holcomb,et al.  Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers , 2009, IEEE Transactions on Computers.

[19]  Ingrid Verbauwhede,et al.  Experimental evaluation of Physically Unclonable Functions in 65 nm CMOS , 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

[20]  Yu Zheng,et al.  SACCI: Scan-Based Characterization Through Clock Phase Sweep for Counterfeit Chip Detection , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  S. S. Young,et al.  Resampling-Based Multiple Testing: Examples and Methods for p-Value Adjustment , 1993 .

[22]  Yu Zheng,et al.  DScanPUF: A Delay-Based Physical Unclonable Function Built Into Scan Chain , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  Y. Hochberg A sharper Bonferroni procedure for multiple tests of significance , 1988 .

[24]  Mark Mohammad Tehranipoor,et al.  Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain , 2014, Proceedings of the IEEE.

[25]  G. Edward Suh,et al.  Physical Unclonable Functions for Device Authentication and Secret Key Generation , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[26]  Jie Zhang,et al.  BoardPUF: Physical Unclonable Functions for printed circuit board authentication , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[27]  Yu Zheng,et al.  ScanPUF: Robust ultralow-overhead PUF using scan chain , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).