A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis

Hardware Trojan Horses have emerged as great threats to modern electronic design and manufacturing practices. Because of their inherent surreptitious nature, test vector generation to detect hardware Trojan horses is a difficult problem. Efficient online detection techniques can be more effective in detection of hardware Trojan horses. In this paper, we propose a low-overhead detection technique which inserts malicious logic detection circuitry at netlist sites chosen by an algorithm that employs an intelligent and accurate analysis of fault propagation through logic gates. Proactive system-level countermeasures can be activated on detection of malicious logic, thereby avoiding disastrous system failure. Experimental results on benchmark circuits show close to 100 percent HTH detection coverage when our proposed technique is employed, as well as acceptable overheads.

[1]  Dhiraj K. Pradhan,et al.  A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications , 1980, IEEE Transactions on Computers.

[2]  Edward J. McCluskey,et al.  Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs , 1984, IEEE Transactions on Computers.

[3]  Niraj K. Jha Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Yervant Zorian,et al.  On-Line Testing for VLSI—A Compendium of Approaches , 1998, J. Electron. Test..

[5]  Paul C. Kocher,et al.  Differential Power Analysis , 1999, CRYPTO.

[6]  John P. Hayes,et al.  Accurate reliability evaluation and enhancement via probabilistic transfer matrices , 2005, Design, Automation and Test in Europe.

[7]  Susmit Jha,et al.  Randomization Based Probabilistic Approach to Detect Trojan Circuits , 2008, 2008 11th IEEE High Assurance Systems Engineering Symposium.

[8]  Michael S. Hsiao,et al.  Guided test generation for isolation and detection of embedded trojans in ics , 2008, GLSVLSI '08.

[9]  J.-F. Naviner,et al.  Reliability of logic circuits under multiple simultaneous faults , 2008, 2008 51st Midwest Symposium on Circuits and Systems.

[10]  Denis Teixeira Franco,et al.  Signal probability for reliability evaluation of logic circuits , 2008, Microelectron. Reliab..

[11]  Tim Güneysu,et al.  Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering , 2009, CHES.

[12]  Swarup Bhunia,et al.  Security against hardware Trojan through a novel application of design obfuscation , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[13]  Bhagirath Narahari,et al.  Providing secure execution environments with a last line of defense against Trojan circuit attacks , 2009, Comput. Secur..

[14]  Christof Paar,et al.  MOLES: Malicious off-chip leakage enabled by side-channels , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[15]  Bhagirath Narahari,et al.  OS support for detecting Trojan circuit attacks , 2009, 2009 IEEE International Workshop on Hardware-Oriented Security and Trust.

[16]  Swarup Bhunia,et al.  Hardware Trojan: Threats and emerging solutions , 2009, 2009 IEEE International High Level Design Validation and Test Workshop.

[17]  Michael S. Hsiao,et al.  A Novel Sustained Vector Technique for the Detection of Hardware Trojans , 2009, 2009 22nd International Conference on VLSI Design.

[18]  Christos A. Papachristou,et al.  MERO: A Statistical Approach for Hardware Trojan Detection , 2009, CHES.

[19]  Miron Abramovici,et al.  Integrated circuit security: new threats and solutions , 2009, CSIIRW '09.

[20]  Swarup Bhunia,et al.  Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection , 2010, CHES.

[21]  Tian Ban,et al.  A simple fault-tolerant digital voter circuit in TMR nanoarchitectures , 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

[22]  Farinaz Koushanfar,et al.  A Survey of Hardware Trojan Taxonomy and Detection , 2010, IEEE Design & Test of Computers.

[23]  Kaushik Roy,et al.  Multiple-parameter side-channel analysis: A non-invasive hardware Trojan detection approach , 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[24]  Debdeep Mukhopadhyay,et al.  Differential Fault Analysis of the Advanced Encryption Standard Using a Single Fault , 2011, WISTP.

[25]  Samuel Nascimento Pagliarini,et al.  Exploring the feasibility of selective hardening for combinational logic , 2012, Microelectron. Reliab..

[26]  Mark Mohammad Tehranipoor,et al.  A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[27]  Siddharth Garg,et al.  Securing Computer Hardware Using 3D Integrated Circuit (IC) Technology and Split Manufacturing for Obfuscation , 2013, USENIX Security Symposium.

[28]  Jeyavijayan Rajendran,et al.  Is split manufacturing secure? , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[29]  Mark Mohammad Tehranipoor,et al.  BISA: Built-in self-authentication for preventing hardware Trojan insertion , 2013, 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[30]  Samuel Nascimento Pagliarini,et al.  Reliability analysis methods and improvement techniques applicable to digital circuits , 2013 .

[31]  Morteza Saheb Zamani,et al.  Neutralizing a design-for-hardware-trust technique , 2013, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013).

[32]  Mark Mohammad Tehranipoor,et al.  Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution , 2013, IEEE Design & Test.

[33]  Simha Sethumadhavan,et al.  FANCI: identification of stealthy malicious logic using boolean functional analysis , 2013, CCS.

[34]  Ruby B. Lee,et al.  Hardware-Enhanced Security for Cloud Computing , 2014, Secure Cloud Computing.

[35]  Brandon Wang,et al.  Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[36]  Giorgio Di Natale,et al.  A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans , 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

[37]  Wayne P. Burleson,et al.  Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware , 2014, 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography.

[38]  Jeyavijayan Rajendran,et al.  Fault Analysis-Based Logic Encryption , 2015, IEEE Transactions on Computers.

[39]  Sayak Ray,et al.  Evaluating the security of logic encryption algorithms , 2015, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[40]  Sylvain Guilley,et al.  Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horses , 2015, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[41]  Debdeep Mukhopadhyay,et al.  Improved Test Pattern Generation for Hardware Trojan Detection Using Genetic Algorithm and Boolean Satisfiability , 2015, CHES.

[42]  Miodrag Potkonjak,et al.  Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications , 2015, Proceedings of the IEEE.

[43]  Yiorgos Makris,et al.  Hardware Trojan Detection in Analog/RF Integrated Circuits , 2016 .

[44]  Wei Zhang,et al.  Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[45]  Giovanni De Micheli,et al.  Emerging Technology-Based Design of Primitives for Hardware Security , 2016, JETC.

[46]  Zhimin Chen,et al.  Hardware Trojan Designs on Basys Fpga Board , .