Energy consumption modeling and optimization for SRAM's
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[1] Evert Seevinck,et al. Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's , 1991 .
[2] A. Tyagi. Energy consumption in multilective and boundary VLSI computations , 1991 .
[3] B. Haroun,et al. Power estimation tool for sub-micron CMOS VLSI circuits , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.
[4] G. Y. Yacoub,et al. An enhanced technique for simulating short-circuit power dissipation , 1989 .
[5] H. Goto,et al. A 3.3-V 12-ns 16-Mb CMOS SRAM , 1992 .
[6] H. Shinohara,et al. A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM , 1983, IEEE Journal of Solid-State Circuits.
[7] Kurt Keutzer,et al. Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] D. N. Smithe,et al. Magic User's Manual. , 1996 .
[9] Doris Schmitt-Landsiedel,et al. Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[10] Kenji Maeguchi,et al. A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell , 1990 .
[11] Richard C. Jaeger,et al. A high-speed clamped bit-line current-mode sense amplifier , 1991 .
[12] Hendrikus J. M. Veendrick,et al. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .
[13] Christer Svensson,et al. Trading speed for low power by choice of supply and threshold voltages , 1993 .
[14] Farid N. Najm,et al. McPOWER: a Monte Carlo approach to power estimation , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.
[15] K. Ishibashi,et al. A 23 ns 4 Mb CMOS SRAM with 0.5 mu A standby current , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.
[16] Anantha P. Chandrakasan,et al. Low-power CMOS digital design , 1992 .
[17] Kunihiko Yamaguchi,et al. High-speed sensing techniques for ultrahigh-speed SRAMs , 1992 .
[18] L. Greggain,et al. Predicting and scaling power consumption in CMOS ASICs , 1989, Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,.
[19] S. Aizaki,et al. A 15 ns 4 Mb CMOS SRAM , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.
[20] D. Schmitt-Landsiedel,et al. Automatic transistor sizing in high performance CMOS logic circuits , 1989, Proceedings. VLSI and Computer Peripherals. COMPEURO 89.
[21] A. Nabavi-Lishi,et al. Delay and bus current evaluation in CMOS logic circuits , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.
[22] Sung-Mo Kang. Accurate simulation of power dissipation in VLSI circuits , 1986 .
[23] Joos Vandewalle,et al. Estimation of typical power of synchronous CMOS circuits using a hierarchy of simulators , 1993 .
[24] K. Anami,et al. A 20 ns 4 Mb CMOS SRAM with hierarchical word decoding architecture , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.
[25] M. Ukita,et al. A 21-mW 4-Mb CMOS SRAM for battery operation , 1991 .
[26] Paul D. Franzon,et al. Energy control and accurate delay estimation in the design of CMOS buffers , 1994 .