Power-Aware Compilation for Register File Energy Reduction

Most power reduction techniques have focused on gating the clock to unused functional units to minimize static power consumption, while system level optimizations have been used to deal with dynamic power consumption. Once these techniques are applied, register file power consumption becomes a dominant factor in the processor. This paper proposes a power-aware reconfiguration mechanism in the register file driven by a compiler. Optimal usage of the register file in terms of size is achieved and unused registers are put into a low-power state. Total energy consumption in the register file is reduced by 65% with no appreciable performance penalty for MiBench benchmarks on an embedded processor. The effect of reconfiguration granularity on energy savings is also analyzed, and the compiler approach to optimize energy results is presented.

[1]  P. Gronowski,et al.  Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[2]  Antonio Gonzalez,et al.  Lazy Retirement: A Power Aware Register Management Mechanism , 2002 .

[3]  Rajiv Gupta,et al.  Profile guided selection of ARM and thumb instructions , 2002, LCTES/SCOPES '02.

[4]  Kaushik Roy,et al.  Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories , 2000, ISLPED '00.

[5]  Trevor Mudge,et al.  The Need for Large Register Files in Integer Codes , 2000 .

[6]  Aviral Shrivastava,et al.  An efficient compiler technique for code size reduction using reduced bit-width ISAs , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[7]  Norman P. Jouppi,et al.  WRL Research Report 93/5: An Enhanced Access and Cycle Time Model for On-chip Caches , 1994 .

[8]  A. Veidenbaum,et al.  Architectural and compiler strategies for dynamic power management in the COPPER project , 2001, 2001 Innovative Architecture for Future Generation High-Performance Processors and Systems.

[9]  Diana Marculescu,et al.  Power aware microarchitecture resource scaling , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[10]  Scott Mahlke,et al.  Scalar program performance on multiple-instruction-issue processors with a limited number of registers , 1992, Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences.

[11]  M. Merten,et al.  A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization , 1999, Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367).

[12]  Alexander V. Veidenbaum,et al.  Energy aware register file implementation through instruction predecode , 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

[13]  Gürhan Küçük,et al.  Energy-Efficient Design of the Reorder Buffer , 2002, PATMOS.

[14]  Javier Zalamea,et al.  Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures , 2004, International Journal of Parallel Programming.

[15]  T. Mudge,et al.  Drowsy caches: simple techniques for reducing leakage power , 2002, Proceedings 29th Annual International Symposium on Computer Architecture.

[16]  Rajesh Gupta,et al.  Profile-based dynamic voltage scheduling using program checkpoints , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[17]  Larry L. Biro,et al.  Power considerations in the design of the Alpha 21264 microprocessor , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[18]  David Ruimy Gonzales.  Micro-RISC architecture for the wireless market , 1999, IEEE Micro.

[19]  Yu Bai,et al.  Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors , 2000, PACS.

[20]  Todd M. Austin,et al.  SimpleScalar: An Infrastructure for Computer System Modeling , 2002, Computer.

[21]  Mahmut T. Kandemir,et al.  Influence of compiler optimizations on system power , 2000, Proceedings 37th Design Automation Conference.

[22]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[23]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[24]  Mark Horowitz,et al.  Energy dissipation in general purpose microprocessors , 1996, IEEE J. Solid State Circuits.

[25]  John C. Gyllenhaal,et al.  A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization , 1999, ISCA.

[26]  Koji Inoue,et al.  High-Performance Low-Power Cache Memory Architectures , 2001 .

[27]  Trevor N. Mudge,et al.  Reducing register ports using delayed write-back queues and operand pre-fetch , 2003, ICS '03.